1. Field of the Invention
The invention relates to a dynamic memory cell for use in a DRAM memory.
2. Description of the Related Art
DRAM memory cells known hitherto have the disadvantage that only the potential of one bit line of a bit line pair is altered during an activation in the time in which the cell charge flows onto the bit line. The potential difference on the bit lines of the bit line pair is amplified by a sense amplifier, in which the potential with the higher charge is increased and the potential with the lower charge is decreased. The divergent separation of the charges on the bit lines of the bit line pair is not completely symmetrical since, proceeding from a center potential, only one of the bit lines is connected to the storage capacitor, so that initially only the charge of one bit line changes during the read-out of the memory cell. This leads to an asymmetrical divergent separation of the charges during amplification (presensing).
This behavior during presensing has the effect that it is not possible to completely preclude the signal coupling between adjacent bit lines of different adjacent bit line pairs with a twisting of the bit lines of the bit line pairs. By contrast the negative influences from the coupling between the bit lines can be virtually precluded with the aid of the twisting of the bit lines in the case of a symmetrical behavior in the case of charge separation in presensing.